nAst1: Progress and Concepts Thread

[robertisaar]

i've been running various versions before i ever started this thread, if that's any indication.

[caffeine]

I've been running 1.05 in my daily driven fiero for about 4 months now but I never did get the idle right (idles rich). Not sure if it has to do with the injectors I'm using though (stock 3500).

[ga2001532]

How can we enable the shift light?

[robertisaar]

assuming you start off with a manual BIN, it should already be enabled. if it's not coming on, either you have a bad bulb, it isn't wired in or the calibration for the light needs corrected.

[ga2001532]

Is their a manual bin I can modify to put on my 2001 grand am pcm to make the light work

[robertisaar]

........ wouldn't know, OBD2 is not my area of expertise.

[caffeine]

Sorry if this is a dumb question, but is the 9396 interchangeable with the 7727 when it comes to the pinouts? And there is no interior version of the 9396?

[robertisaar]

yes, 7727 and 9396 use the same connectors. if you pop them open and compare them, you'll see that they're identical except for i think 1 IC, that's the 2K of SRAM mapped from 1800-1FFF.

no non-weatherproof version was made.

[brian89gp]

well, here is 1.06.
i need my damn MEMCAL back to test the ability to use 64KB BINs(i'm not sure how well my G3 adapter is reacting to it) after some internal modifications to the PCM. GM, for whatever reason, connected 5V to the highest address pin on the MEMCAL connector(essentially only allowing 8000-FFFF to be usable on the PROM, instead of the potential 0000-FFFF range not counting the adresses taken up by the RAM and registers), so i did a quick mod to remove the 5V applied and have it switch as necessary, but i haven't been able to test it yet. this is pretty much a requirement to move much further forward, since PROM space has quickly run out.

Theoretically, would any addresses not in use for IO, SRAM (9396), etc then address #0000-#7FFF on the PROM? How would it handle overlap, eg address #00C6 in RAM and not #00C6 in PROM?

Been dissasembling on 12p yet? Some good idea's there.

[robertisaar]

that's the idea. i assume the CS circuit would be what determines which external device is read for any given address.

12p? sounds like an aussy setup(possibly non-factory)? i know some of those guys are wizards with code.

[brian89gp]

That would be cool if it indeed works that way.

It is an aussy setup. They take the possibilities of using a NVSRAM module in place of an EEPROM/Flash chip to new levels.

[robertisaar]

that's right..... they essentially flash portions the NVRAM instead of the entire block(except for the initial burn in a programmer), essentially like what is done with OBD2 in case of a bad flash, so it doesn't kill the OS.

they're still running with a 32KB BIN as well... i do need to see what all fat i can trim out of the stock cals.... factory test never gets used, neither does any of the HUD stuff, it just sits there and takes up space and processing cycles to bypass it.

[brian89gp]

More so it looks like the code itself can write to the main program space, eg the VE Learn feature. Turn of INT/BLM learning and instead have it directly modify (and save) to the VE tables directly.

[robertisaar]

while extremely interesting(and surprisingly easy to impliment), i don't think i would want that to happen without my inspection and approval...... that's just asking for a bad O2 sensor to take out the engine. if some significant limits were put in place(can only adjust so far up or down), i could see it being useful and relatively safe.

[brian89gp]

Spent a little too much time researching the hardware side of the P4 ECM today... Anyways, after reading about adding SRAM and NVSRAM modules it looks like you might need to have additional hardware in order to use any part of the other 32k address space. All the chips on the 16 bit bus look to have CS/CE (chip select/chip enable) pins and OE (output enable) pins or some other similar method to select a particular chip to read/write from, I'm not sure that simply adding the A15 wire will do anything as the 68HC11 probably has the EEPROM address space hard coded as far as CE/OE goes. Either way, the CE and OE need to be drawn low in order for the EEPROM chip to output anything onto the bus.

It should be possible to either use a 64k chip and manually (through hardware) map certain address ranges or use a second PROM/NVSRAM chip and map it to those addresses. The implementation of the custom SRAM mod to the '730 which turned into the 4k NVSRAM mod goes into this somewhat.

I really hope I am wrong and that GM was lazy and it somehow works, but if it doesn't there still appears to be other ways to get the additional space.